The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2016

Filed:

Oct. 14, 2011
Applicants:

Sivaprakasam Sunder, Cupertino, CA (US);

Kirk Schollman, Plano, TX (US);

Inventors:

Sivaprakasam Sunder, Cupertino, CA (US);

Kirk Schollman, Plano, TX (US);

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); G06F 17/5031 (2013.01); G06F 2217/62 (2013.01);
Abstract

A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters.


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Sunder, Sivaprakasam. (2016). Multi-mode multi-corner clocktree synthesis (U.S. Patent No. 9310831). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9310831

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