The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Mar. 15, 2012
Applicants:

Tsung-yuan Chen, Taoyuan County, TW;

Shu-sheng Chiang, Taipei, TW;

Inventors:

Tsung-Yuan Chen, Taoyuan County, TW;

Shu-Sheng Chiang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 3/10 (2006.01); H05K 3/04 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 3/107 (2013.01); H05K 3/045 (2013.01); H05K 3/423 (2013.01); H05K 3/426 (2013.01); H05K 2201/0376 (2013.01); H05K 2201/09036 (2013.01); H05K 2201/09563 (2013.01); Y10T 29/49155 (2015.01); Y10T 29/49165 (2015.01);
Abstract

A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively.


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