The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Nov. 03, 2014
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventor:

Seigo Namioka, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 21/7684 (2013.01); H01L 21/76801 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 21/76883 (2013.01); H01L 27/10855 (2013.01); H01L 27/10894 (2013.01); H01L 29/4175 (2013.01);
Abstract

In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR. The eDRAM further includes: a capacitive plug electrode coupled to the drain plug electrode; a bit line coupled to the source plug electrode; a stopper film covering the bit line; and a capacitive element that is formed over the stopper film and has a first electrode, a dielectric film, and a second electrode. The first electrode is coupled to the capacitive plug electrode, and the height of the capacitive plug electrode and that of the bit line are equal to each other.


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