The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2016
Filed:
Mar. 06, 2015
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 21/78 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/95 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 21/76897 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49827 (2013.01); H01L 24/11 (2013.01); H01L 24/81 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 2224/1182 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01);
Abstract
A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.