The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Jun. 18, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Richard S. Graf, Gray, ME (US);

Ezra D. B. Hall, Richmond, VT (US);

Vibhor Jain, Essex Junction, VT (US);

Jack R. Smith, South Burlington, VT (US);

Sebastian T. Ventrone, South Burlington, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 21/768 (2006.01); H01L 21/56 (2006.01); H01L 23/38 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4871 (2013.01); H01L 21/56 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 23/3675 (2013.01); H01L 23/38 (2013.01);
Abstract

Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.


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