The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2016

Filed:

Nov. 13, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

He Ren, San Jose, CA (US);

Chia-Ling Kao, San Jose, CA (US);

Sean Kang, San Ramon, CA (US);

Jeremiah T P Pender, San Jose, CA (US);

Srinivas D. Nemani, Sunnyvale, CA (US);

Mehul B. Naik, San Jose, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/3065 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/308 (2013.01); H01L 21/0234 (2013.01); H01L 21/02063 (2013.01); H01L 21/0332 (2013.01); H01L 21/3065 (2013.01); H01L 21/30604 (2013.01); H01L 21/31116 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01); H01L 21/76807 (2013.01);
Abstract

Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.


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