Method and apparatus for fast low skew phase generation for multiplexing signals on a multi-fpga prototyping system

Abstract

An apparatus and method is described for low skew phase generation for multiplexing signals using limited global low skew lines on a multiple FPGA system. The apparatus includes a reference clock programmed to generate a clock signal and programmable logic devices. The programmable logic devices include I/O terminals, combinational logic coupled to the I/O terminals, programmable logic coupled to the combinational logic, a phase generator programmed to receive the clock signal from the reference clock and to generate a phase clock based on the clock signal and a plurality of phase enable signals based on the phase clock, low skew lines to distribute the phase enables with minimal skew caused by routing delays, and flip-flops programmed to have a clock input driven by the phase clock, a data input coupled to ground, and a data output coupled to the combinational logic. Furthermore, synchronous preset inputs of the flip-flops receive the low skew phase enable signals to control transmission design signals by one of the I/O terminal.