The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2016
Filed:
Sep. 12, 2012
Peilin Wang, Beijing, CN;
Jingjing Chen, Beijing, CN;
Edouard D. DE Fresart, Tempe, AZ (US);
Pon Sung Ku, Gilbert, AZ (US);
Wenyi LI, Beijing, CN;
Ganming Qin, Chandler, AZ (US);
Peilin Wang, Beijing, CN;
Jingjing Chen, Beijing, CN;
Edouard D. de Fresart, Tempe, AZ (US);
Pon Sung Ku, Gilbert, AZ (US);
Wenyi Li, Beijing, CN;
Ganming Qin, Chandler, AZ (US);
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET () to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.