The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Oct. 18, 2013
Applicant:

Transphorm Inc., Goleta, CA (US);

Inventors:

Primit Parikh, Goleta, CA (US);

James Honea, Santa Barbara, CA (US);

Carl C. Blake, Jr., Fountain Valley, CA (US);

Robert Coffie, Camarillo, CA (US);

Yifeng Wu, Goleta, CA (US);

Umesh Mishra, Montecito, CA (US);

Assignee:

Transphorm Inc., Goleta, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H01L 27/088 (2006.01); H01L 21/8258 (2006.01); H01L 27/06 (2006.01); H03K 17/567 (2006.01); H01L 23/495 (2006.01); H01L 25/16 (2006.01); H01L 23/64 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0883 (2013.01); H01L 21/8258 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 25/165 (2013.01); H01L 27/0605 (2013.01); H03K 17/567 (2013.01); H01L 23/642 (2013.01); H01L 23/647 (2013.01); H01L 25/18 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48195 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48257 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/30107 (2013.01);
Abstract

An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.


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