The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Apr. 24, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kevin S. Petrarca, Newburgh, NY (US);

Stuart A. Sieg, Albany, NY (US);

Theodorus E. Standaert, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/033 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/02123 (2013.01); H01L 21/0337 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/31051 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/823481 (2013.01); H01L 27/0924 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.


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