The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Dec. 15, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Dzung Nguyen, Freemont, CA (US);

Luyen T. Vu, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 29/02 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G11C 29/10 (2006.01);
U.S. Cl.
CPC ...
G11C 29/08 (2013.01); G01R 31/3177 (2013.01); G01R 31/318536 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 29/02 (2013.01); G11C 29/10 (2013.01);
Abstract

Briefly, in accordance with one or more embodiments, an apparatus to test a semiconductor device comprises a controller configured to perform one or more tests on the semiconductor device, a reduce low pin count (RLPC) circuit configured to write data to the semiconductor device or read data from the semiconductor device at a double data rate (DDR) with respect to a single data rate (SDR), and pad logic to couple to the semiconductor device, the pad logic configured to provide a trimmable data access time from clock (tAC) signal to select different access times of a single data rate (SDR) or a double data rate (DDR) mode of operation, wherein a loading time or an unloading time of the semiconductor device being tested, or a combination thereof, is reduced when a DDR mode is selected.


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