The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Jun. 25, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Lev Makovsky, Hafia, IL;

Zeev Sperber, Zichron Yackov, IL;

Efraim Rotem, Haifia, IL;

Nir Rosenzweig, Givat Ella, IL;

Stanislav Shwartsman, Hafia, IL;

Raanan Sade, Kibutz Sarid, IL;

Igor Yanover, Yokneam Illit, IL;

Gavri Berger, Hafia, IL;

Tomer Weiner, Mahane Miryam, IL;

Ron Gabor, Ra'anana, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 9/54 (2006.01); G06F 9/30 (2006.01); G06F 9/48 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 9/542 (2013.01); G06F 1/3206 (2013.01); G06F 9/30 (2013.01); G06F 9/4856 (2013.01);
Abstract

In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.


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