The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

May. 23, 2013
Applicant:

Rambus Inc., Sunnyvale, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

Craig E. Hampel, Los Altos, CA (US);

Wayne S. Richardson, Saratoga, CA (US);

Chad A. Bellows, Birmingham, MI (US);

Lawrence Lai, San Jose, CA (US);

Assignee:

Rambus Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01); G11C 11/4076 (2006.01); G11C 11/4097 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0613 (2013.01); G06F 3/0673 (2013.01); G11C 7/1006 (2013.01); G11C 7/1042 (2013.01); G11C 7/22 (2013.01); G11C 8/06 (2013.01); G11C 11/4076 (2013.01); G11C 11/4097 (2013.01);
Abstract

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.


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