The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Jul. 03, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nicholas P. Cowley, Wroughton, GB;

Chi Man Kan, Swindon, GB;

Ruchir Saraswat, Swindon, GB;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 3/46 (2015.01); H04L 1/20 (2006.01); H03D 13/00 (2006.01); H04B 3/14 (2006.01);
U.S. Cl.
CPC ...
H04L 1/205 (2013.01); H03D 13/003 (2013.01); H04B 3/146 (2013.01);
Abstract

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.


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