The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Jul. 18, 2014
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Yury Gaknoki, San Jose, CA (US);

David Kung, Foster City, CA (US);

Michael Yue Zhang, Mountain View, CA (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/335 (2006.01); H02M 1/08 (2006.01); H02M 1/00 (2007.01);
U.S. Cl.
CPC ...
H02M 3/33515 (2013.01); H02M 1/08 (2013.01); H02M 3/33523 (2013.01); H02M 2001/0025 (2013.01);
Abstract

An example controller circuit includes a feedback sampling circuit, an oscillator, a drive logic, and a false sampling prevention circuit. The feedback sampling circuit generates a sample signal in response to a sampling of a feedback signal. The oscillator generates an on-time signal that transitions from a first logic state to a second logic state during each period of the on-time signal. The drive logic controls a switch to regulate the output of a power converter. The drive logic turns on the switch to end an off-time of the switch in response to the on-time signal transitioning from the first logic state to the second logic state. The false sampling prevention circuit prevents the on-time signal from transitioning from the first logic state to the second logic state to extend the off-time of the switch until a sampling complete signal indicates that sampling of the feedback signal is complete.


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