The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Dec. 12, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

John S. Guzek, Chandler, AZ (US);

Debendra Mallik, Chandler, AZ (US);

Sasha N. Oster, Chandler, AZ (US);

Timothy E. McIntosh, Phoenix, AZ (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/481 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/17 (2013.01); H01L 25/50 (2013.01); H01L 23/49816 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16235 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/182 (2013.01);
Abstract

Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.


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