The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Dec. 28, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ruchir Saraswat, Swindon, GB;

Uwe Zillmann, Braunschweig, DE;

Andre Schaefer, Braunschweig, DE;

Tor Lund-Larsen, Braunschweig, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2006.01); H01L 27/06 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/642 (2013.01); H01L 23/645 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6666 (2013.01); H01L 2223/6672 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Resonant clocking for three-dimensional stacked devices. An embodiment of an apparatus includes a stack including integrated circuit dies; and through silicon vias through at least one of the dies, wherein at least a first through silicon via of the through silicon vias includes a capacitive structure or an inductive structure, the first through silicon via being formed in a first die of the plurality of dies. The apparatus includes a resonant circuit, the first through silicon via used as a first circuit element of the resonant circuit.


Find Patent Forward Citations

Loading…