The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2016
Filed:
Mar. 11, 2014
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Daniel J. Chu, Folsom, CA (US);
Kiran Pangal, Fremont, CA (US);
Nathan R. Franklin, San Mateo, CA (US);
Prashant S. Damle, Santa Clara, CA (US);
Hu Chaohong, San Jose, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 11/5678 (2013.01); G11C 13/0004 (2013.01); G11C 13/0033 (2013.01); G11C 13/0035 (2013.01); G11C 2013/0052 (2013.01);
Abstract
The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.