The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Jul. 08, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ming-Zhang Kuo, Qionglin Township, TW;

Cheng-Chung Lin, Hsin-Chu, TW;

Ho-Chieh Hsieh, Hsin-Chu, TW;

Kuo Feng Tseng, Taipei, TW;

Sang Hoo Dhong, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/417 (2006.01); G11C 5/02 (2006.01); G11C 11/4076 (2006.01); G11C 5/06 (2006.01); G11C 7/00 (2006.01); G11C 7/08 (2006.01); G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 11/4094 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/148 (2013.01); G11C 5/025 (2013.01); G11C 5/06 (2013.01); G11C 7/08 (2013.01); G11C 7/12 (2013.01); G11C 11/4076 (2013.01); G11C 11/4094 (2013.01); G11C 11/417 (2013.01);
Abstract

A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.


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