Memory controller half-clock delay adjustment

Abstract

A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.