The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Oct. 01, 2014
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Taranjit Singh Kukal, Delhi, IN;

Steven Durrill, Campbell, CA (US);

Utpal Bhattacharyya, Noida, IN;

Amit Sharma, New Delhi, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5009 (2013.01);
Abstract

Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.


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