The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2016

Filed:

Mar. 11, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Qiong Cai, Barcelona, ES;

Dyer Rolan, Barcelona, ES;

Blas Cuesta, Barcelona, ES;

Ferad Zyulkyarov, Barcelona, ES;

Serkan Ozdemir, Barcelona, ES;

Marios Nicolaides, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/12 (2013.01); G06F 12/122 (2013.01); G06F 2212/69 (2013.01); G06F 2212/7211 (2013.01);
Abstract

Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.


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