The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Jul. 03, 2012
Applicants:

Huaxiang Yin, Beijing, CN;

Changliang Qin, Beijing, CN;

Xiaolong MA, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Dapeng Chen, Beijing, CN;

Inventors:

Huaxiang Yin, Beijing, CN;

Changliang Qin, Beijing, CN;

Xiaolong Ma, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Dapeng Chen, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/1037 (2013.01); H01L 29/1095 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01);
Abstract

The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.


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