The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

May. 16, 2014
Applicants:

Young Seog Kim, Pleasanton, CA (US);

Kuoyuan Hsu, San Jose, CA (US);

Jacklyn Chang, San Ramon, CA (US);

Inventors:

Young Seog Kim, Pleasanton, CA (US);

Kuoyuan Hsu, San Jose, CA (US);

Jacklyn Chang, San Ramon, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01); G06F 17/50 (2006.01); G11C 15/04 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G11C 15/04 (2013.01); H03K 19/20 (2013.01);
Abstract

A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot.


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