The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Dec. 02, 2004
Applicants:

Sanjoy K. Mondal, San Marcos, TX (US);

Rajesh B. Patel, Austin, TX (US);

Lawrence O. Smith, Beaverton, OR (US);

Inventors:

Sanjoy K. Mondal, San Marcos, TX (US);

Rajesh B. Patel, Austin, TX (US);

Lawrence O. Smith, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 9/30 (2006.01); G06F 12/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0862 (2013.01); G06F 9/3016 (2013.01); G06F 9/30149 (2013.01); G06F 9/30181 (2013.01); G06F 12/10 (2013.01); G06F 12/1027 (2013.01); G06F 12/0888 (2013.01);
Abstract

A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.


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