The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Mar. 17, 2014
Applicants:
Chip Integration Tech. Co., Ltd., Zhubei, Hsinchu County, TW;
Qinhai Jin, Zhubei, Hsinchu County, TW;
Inventor:
Qinhai Jin, Zhubei, TW;
Assignee:
CHIP INTEGRATION TECH. CO., LTD., Zhubei, Hsinchu County, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/747 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01); H01L 29/74 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/747 (2013.01); H01L 29/407 (2013.01); H01L 29/42308 (2013.01); H01L 29/66378 (2013.01); H01L 29/742 (2013.01);
Abstract
A structure of trench MOS rectifier and a method of forming the same are disclosed including a plurality of trenches formed in the n− drift epitaxial layer, a plurality of MOS structure formed on the substrate either in discrete islands or in rows. Asides the MOS gates there are source regions formed under the mesas. A top metal served as an anode is then formed on the resulted front surface connecting the MOS gates and the adjacent source regions.