The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
Dec. 18, 2013
Applicant:
Intermolecular, Inc., San Jose, CA (US);
Inventors:
Yun Wang, San Jose, CA (US);
Imran Hashim, Saratoga, CA (US);
Assignee:
Intermolecular, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/66 (2006.01); G11C 16/10 (2006.01); G11C 11/02 (2006.01); H01L 27/24 (2006.01); G11C 11/56 (2006.01); H01L 27/10 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); G11C 11/02 (2013.01); G11C 11/5685 (2013.01); G11C 13/0007 (2013.01); G11C 13/0035 (2013.01); G11C 13/0069 (2013.01); G11C 16/10 (2013.01); H01L 27/101 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1266 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); G11C 13/0004 (2013.01); G11C 2013/0071 (2013.01); G11C 2213/79 (2013.01); H01L 45/06 (2013.01);
Abstract
Designs and programming schemes can be used to form memory arrays having low power, high density and good data retention. High resistance interconnect lines can be used to partition the memory array can be partitioned into areas of high data retention and areas of low data retention. Variable gate voltages can be used in control transistors to store memory values having different data retention characteristics.