The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9275014 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 01, 2016

Filed:

Mar. 13, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Raheel Khan, Tustin, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/14 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 7/544 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 17/142 (2013.01); G06F 7/5443 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/3887 (2013.01); G06F 9/3897 (2013.01); G06F 15/8053 (2013.01); G06F 2207/382 (2013.01);
Abstract

Vector processing engines (VPEs) having programmable data path configurations for providing multi-mode Radix-2butterfly vector processing circuits. Related vector processors, systems, and methods are also disclosed. The VPEs disclosed herein include a plurality of vector processing stages each having vector processing blocks that have programmable data path configurations for performing Radix-2butterfly vector operations to perform Fast Fourier Transform (FFT) vector processing operations efficiently. The data path configurations of the vector processing blocks can be programmed to provide different types of Radix-2butterfly vector operations as well as other arithmetic logic vector operations. As a result, fewer VPEs can provide desired Radix-2butterfly vector operations and other types arithmetic logic vector operations in a vector processor, thus saving area in the vector processor while still retaining vector processing advantages of fewer register writes and faster vector instruction execution times over scalar processing engines.


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