The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Jun. 24, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

David D. Bar-On, Givat Ella, IL;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 10/80 (2013.01); H03M 13/29 (2006.01); H03M 13/19 (2006.01); H03M 13/31 (2006.01);
U.S. Cl.
CPC ...
H04B 10/80 (2013.01); H03M 13/2906 (2013.01); H03M 13/19 (2013.01); H03M 13/31 (2013.01);
Abstract

Techniques are disclosed for detecting image depth in three-dimensional (3-D) surface imaging. The disclosed techniques can be used, for example, to provide structured light encoded with a coded word that includes error-correcting code (ECC). The ECC is effectively configured to detect and correct data errors as may result, for example, from the presence of ambient light and/or camera-noise-causing errors during imaging. In an example case, the coded word is a 15-bit pattern provided in a 3×5 matrix and including: (1) nine data bits of disparity code; (2) five ECC bits for correcting an error and detecting two errors; and (3) one 8-bit/10-bit encoding bit to ensure the presence of a transient pixel in the data for white threshold level detection. Greater or lesser bit quantities and varied bit partitioning matrices can be provided, as desired. In some cases, imaging robustness and/or power usage can be improved using the disclosed techniques.


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