The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2016
Filed:
Mar. 24, 2014
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Alex Kalnitsky, San Francisco, CA (US);
Chung-Long Chang, Hsinchu, TW;
Yung-Chih Tsai, Jhudong Township, TW;
Tsung-Yu Yang, Zhubei, TW;
Keng-Yu Chen, Tainan, TW;
Yong-En Syu, Tainan, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.