The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Mar. 04, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Raguram Damodaran, Raleigh, NC (US);

Abhijeet Ashok Chachad, Plano, TX (US);

Jonathan (Son) Hung Tran, Murphy, TX (US);

David Matthew Thompson, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/12 (2006.01); G06F 12/10 (2006.01); G06F 7/483 (2006.01); G06F 9/30 (2006.01); H03M 13/35 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06F 13/18 (2006.01); H03K 19/00 (2006.01); G06F 1/32 (2006.01); H03K 21/00 (2006.01); G06F 12/02 (2006.01); G06F 12/08 (2006.01); G06F 13/364 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 1/3296 (2013.01); G06F 7/483 (2013.01); G06F 9/3012 (2013.01); G06F 11/1064 (2013.01); G06F 12/0246 (2013.01); G06F 12/0811 (2013.01); G06F 12/12 (2013.01); G06F 13/1605 (2013.01); G06F 13/18 (2013.01); H03K 19/0016 (2013.01); H03K 21/00 (2013.01); H03M 13/2903 (2013.01); H03M 13/353 (2013.01); G06F 13/1652 (2013.01); G06F 13/1657 (2013.01); G06F 13/1663 (2013.01); G06F 13/364 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/221 (2013.01); G06F 2212/2532 (2013.01); G06F 2212/283 (2013.01); G06F 2212/69 (2013.01); Y02B 60/1214 (2013.01); Y02B 60/1285 (2013.01); Y02B 60/32 (2013.01);
Abstract

This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.


Find Patent Forward Citations

Loading…