The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

Aug. 29, 2014
Applicants:

Anis M. Jarrar, Austin, TX (US);

John M. Boyer, Austin, TX (US);

Saji George, Austin, TX (US);

David R. Tipple, Leander, TX (US);

Inventors:

Anis M. Jarrar, Austin, TX (US);

John M. Boyer, Austin, TX (US);

Saji George, Austin, TX (US);

David R. Tipple, Leander, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 3/037 (2006.01); H03K 19/0175 (2006.01); H03K 19/20 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); G06F 11/079 (2013.01); G06F 11/0751 (2013.01); G06F 11/0793 (2013.01); H03K 3/0372 (2013.01); H03K 19/0175 (2013.01); H03K 19/20 (2013.01);
Abstract

A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.


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