The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Oct. 30, 2012
Applicant:
Globalfoundries Inc., Grand Cayman, KY (US);
Inventors:
Daniel T. Pham, Clifton Park, NY (US);
Robert J. Miller, Yorktown Heights, NY (US);
Kungsuk Maitra, San Jose, CA (US);
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/26506 (2013.01); H01L 29/66795 (2013.01); H01L 29/7842 (2013.01);
Abstract
Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.