The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Jan. 16, 2015
AU Optronics Corp., Hsin-Chu, TW;
Yi-Chen Chung, Hsin-Chu, TW;
Chia-Yu Chen, Hsin-Chu, TW;
Hui-Ling Ku, Hsin-Chu, TW;
Yu-Hung Chen, Hsin-Chu, TW;
Chi-Wei Chou, Hsin-Chu, TW;
Fan-Wei Chang, Hsin-Chu, TW;
Hsueh-Hsing Lu, Hsin-Chu, TW;
Hung-Che Ting, Hsin-Chu, TW;
AU Optronics Corp., Science-Based Industrial Park, Hsin-Chu, TW;
Abstract
The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.