The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Sep. 23, 2014
Integrated Silicon Solution (Shanghai), Inc., Shanghai, CN;
Yoh Tz Chang, Shanghai, CN;
Kai Tao, Shanghai, CN;
INTEGRATED SILICON SOLUTION (SHANGHAI), INC., Shanghai, CN;
Abstract
The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of −7V˜−10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC−6.5V˜VCC−4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V. In full consideration of factors including the chip manufacturing process, chip circuit design, chip quality and cost, optimal operating conditions fit for erasing, reading and programming, a NOR-type embedded 2T PMOS flash memory are determined.