Dynamically configurable sram cell for low voltage operation

Abstract

An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of main storage transistors for maintaining the main terminal at the reference voltage corresponding to the stored logic value, and a set of complementary storage transistors to maintain the complementary terminal at the reference voltage corresponding to the complement of the stored logic value—a main access transistor and a complementary access transistor for accessing the main terminal and the complementary terminal, respectively. The memory device may further include biasing means for modifying a value of a threshold voltage of at least one of the main transistors to a first threshold voltage value or to a second threshold voltage value and for modifying a threshold voltage value of at least one of the complementary transistors to the second threshold voltage value or to the first threshold voltage value during a write operation of the first logic value or of the second logic value, respectively, in the memory cell.