The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2016

Filed:

May. 08, 2013
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Alexander J. Branover, Chesnut Hill, MA (US);

Ashish Jain, Austin, TX (US);

Ann M. Ling, Folscom, CA (US);

Maurice B. Steinman, Marlborough, MA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/20 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/206 (2013.01); G06F 1/324 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/1275 (2013.01); Y02B 60/1285 (2013.01); Y02B 60/32 (2013.01);
Abstract

An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components.


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