Handling slower scan outputs at optimal frequency

Abstract

An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements. Each packing element includes k number of flip-flops. Each flip-flop of the k number of flip-flops receives a scan output of the M scan outputs and a phase-shifted scan clock of the k number of phase-shifted scan clocks, and generates a slow scan output of the kM slow scan outputs.