The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Mar. 31, 2014
Applicant:

Stmicroelectronics International N.v., Amsterdam, NL;

Inventors:

Pratap Narayan Singh, Chahania Chandauli, IN;

Ashish Sharma Kumar, Ghaziabad, IN;

Chandrajit Debnath, Greater Noida, IN;

Rakesh Malik, Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/462 (2013.01); H03M 1/125 (2013.01); H03M 1/00 (2013.01); H03M 1/0695 (2013.01); H03M 1/12 (2013.01);
Abstract

An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.


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