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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9257539 B1

PDFFull Text
Date of Patent:
Feb. 09, 2016

Filed:

Dec. 10, 2014

Method for manufacturing transistor and associated device

Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Rita Rooyackers, Kessel-lo, BE;

Nadine Collaert, Blanden, BE;

Geert Eneman, Balen, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:

Knobbe Martens Olson & Bear, LLP

Primary Examiner:

Hoang-Quan Ho

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 21/336 (2006.01); H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6681 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/7853 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.

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