The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Oct. 27, 2011
Applicants:

I-shan Sun, San Jose, CA (US);

Rick Carlton Jerome, Indialantic, FL (US);

Francois Hebert, San Mateo, CA (US);

Inventors:

I-Shan Sun, San Jose, CA (US);

Rick Carlton Jerome, Indialantic, FL (US);

Francois Hebert, San Mateo, CA (US);

Assignee:

Intersil Americas LLC, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 23/48 (2006.01); H01L 23/535 (2006.01); H01L 21/74 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66204 (2013.01); H01L 21/743 (2013.01); H01L 23/481 (2013.01); H01L 23/535 (2013.01); H01L 27/0688 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.


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