The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Feb. 25, 2014
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Seung Taek Yang, Seoul, KR;

Jong Hoon Kim, Suwon-si, KR;

Tac Keun Oh, Seoul, KR;

Song Na, Jeonju-si, KR;

Assignee:

SK HYNIX INC., Icheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 25/50 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3192 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/92224 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1441 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15788 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01);
Abstract

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.


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