The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9257310 B1

Date of Patent:

Feb. 09, 2016

Filed:

Jun. 24, 2013

Method of manufacturing circuit board and chip package and circuit board manufactured by using the method

Applicant:

Haesung Ds Co., Ltd., Changwon-Si, KR;

Inventor:

Sang-Min Lee, Changwon, KR;

Assignee:

HAESUNG DS CO., LTD., Changwon-si, KR;

Attorney:

Sughrue Mion, PLLC

Primary Examiner:

Selim Ahmed

Int. Cl.

CPC ...

H01L 21/52 (2006.01); H05K 3/46 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H05K 3/00 (2006.01); H01L 23/053 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H05K 1/03 (2006.01); H05K 3/42 (2006.01);

U.S. Cl.

CPC ...

H01L 21/52 (2013.01); H01L 23/145 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 25/0657 (2013.01); H05K 3/002 (2013.01); H05K 3/4697 (2013.01); H01L 23/053 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/48 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/0651 (2013.01); H01L 2924/00014 (2013.01); H05K 1/0366 (2013.01); H05K 1/0373 (2013.01); H05K 3/429 (2013.01); H05K 3/4602 (2013.01); H05K 2201/09118 (2013.01); H05K 2201/09536 (2013.01); H05K 2201/09845 (2013.01); H05K 2203/0554 (2013.01);

Abstract

Provided is a method of manufacturing a circuit board. The method includes: preparing a base substrate including a core layer and a first conductive layer that is formed on at least one surface of the core layer and includes an internal circuit pattern; forming a build-up material to cover the first conductive layer; forming in the build-up material at least one cavity through which the core layer and the first conductive layer are exposed; forming a laminated body by curing the build-up material in which the at least one cavity is formed; and forming a second conductive layer including an external circuit pattern on an outer surface of the laminated body.

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