The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Feb. 27, 2015
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-ken, JP;

Inventors:

Takashi Sato, Nagano, JP;

Ruofan Tang, Nagano, JP;

Assignee:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/12 (2006.01); H05K 1/02 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0269 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/544 (2013.01); H05K 1/115 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54433 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01);
Abstract

A wiring substrate includes wiring layers and insulation layers alternately stacked. Via holes are formed in the insulation layers. First via wirings are formed in the via holes to electrically connect the wiring layers to one another. Through holes extend through a lowermost one of the insulation layers in a thickness direction. The lowermost insulation layer covers a lowermost one of the wiring layers. Second via wirings are formed in the through holes to define an identification mark that is identifiable as a specific shape including a character, a symbol, or a combination thereof. A lower surface of each of the second via wirings is exposed from a lower surface of the lowermost insulation layer and is flush with a lower surface of the lowermost wiring layer.


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