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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9252244 B1

PDFFull Text
Date of Patent:
Feb. 02, 2016

Filed:

Sep. 26, 2014

Methods of selectively growing source/drain regions of fin field effect transistor and method of manufacturing semiconductor device including a fin field effect transistor

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

JinBum Kim, Seoul, KR;

Seong Hoon Jeong, Seongnam-si, KR;

Jeon Il Lee, Suwon-si, KR;

Seokhoon Kim, Suwon-si, KR;

Kwan Heum Lee, Suwon-si, KR;

Choeun Lee, Pocheon-si, KR;

Yu-Jin Pyo, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Mary Wilczewski

Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/161 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/0223 (2013.01); H01L 21/02252 (2013.01); H01L 29/161 (2013.01); H01L 29/517 (2013.01); H01L 29/6656 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 27/1211 (2013.01); H01L 29/785 (2013.01);
Abstract

The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.

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