The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Dec. 07, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Qiuxia Xu, Beijing, CN;

Gaobo Xu, Beijing, CN;

Huajie Zhou, Beijing, CN;

Huilong Zhu, Poughkeepsie, NY (US);

Dapeng Chen, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/265 (2006.01); H01L 21/268 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823857 (2013.01); H01L 21/0206 (2013.01); H01L 21/02301 (2013.01); H01L 21/02304 (2013.01); H01L 21/265 (2013.01); H01L 21/268 (2013.01); H01L 21/28088 (2013.01); H01L 21/28176 (2013.01); H01L 21/28185 (2013.01); H01L 21/28194 (2013.01); H01L 21/28568 (2013.01); H01L 21/324 (2013.01); H01L 21/32139 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 29/1066 (2013.01); H01L 29/42364 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66477 (2013.01); H01L 29/66575 (2013.01); H01L 29/513 (2013.01); H01L 29/665 (2013.01);
Abstract

A method for manufacturing a semiconductor device that comprises two opposite types of MOSFETs formed on one semiconductor substrate, comprising: defining an active region for each of the MOSFETs on the semiconductor substrate; forming an interfacial oxide layer on a surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interfacial oxide layer; forming a metal gate layer on the high-K gate dielectric layer; implanting dopant ions in the metal gate layer; forming a Poly-Si layer on the metal gate layer; patterning the Poly-Si layer, the metal gate layer, the high-K gate dielectric layer and the interfacial oxide layer to form a plurality of gate stack structures; forming a plurality of gate spacer surrounding each of the plurality of gate stack structures; and forming a plurality of S/D regions. During activation annealing for forming the S/D regions, the dopant ions implanted in the metal gate layer diffuse and accumulate at an upper interface of the high-K gate dielectric layer to change the characteristics of the metal gates, and at a lower interface of the high-K gate dielectric layer to form electric dipoles with appropriate polarities by interfacial reaction, so as to realize adjusting of the effective work functions of the metal gates of the opposite types of MOSFETs, respectively.


Find Patent Forward Citations

Loading…