The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Aug. 04, 2014
Applicant:

Stmicroelectronics Pte Ltd, Singapore, SG;

Inventor:

Yonggang Jin, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 21/56 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 21/4803 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49861 (2013.01); H01L 25/072 (2013.01); H01L 25/50 (2013.01);
Abstract

One or more embodiments are directed to a system-in-package (SiP) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer. Furthermore, prior to setting or curing, the encapsulation layer is able to flow between the semiconductor chips and the interposer to provide further mechanical support for the semiconductor chips. Thus, the process for forming the SiP is reduced, resulting in a faster processing time and a lower cost. Additionally, one or more embodiments described herein reduce or eliminate warpage of the interposer.


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