The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Feb. 11, 2009
Applicants:

Vijay Karamcheti, Los Altos, CA (US);

Kumar Ganapathy, Los Altos, CA (US);

Inventors:

Vijay Karamcheti, Los Altos, CA (US);

Kumar Ganapathy, Los Altos, CA (US);

Assignee:

Virident Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 7/78 (2006.01); G06F 12/02 (2006.01); G11C 16/04 (2006.01); G06F 17/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0408 (2013.01); G06F 7/78 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 17/30477 (2013.01); G06F 12/0207 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7208 (2013.01); Y02B 60/1225 (2013.01);
Abstract

In one embodiment of the invention, a method of upgrading main memory in a computer system is disclosed. The method includes plugging a plurality of two dimensional memory modules into a plurality of memory module sockets and coupling a master memory controller between one or more processors and the plurality of memory modules. Each of the two dimensional memory modules includes memory in a plurality of memory slices and a plurality of slave memory controllers respectively coupled to the memory in the plurality of memory slices. According, the upgrading method further includes buffering and transposing data between a column by column format for the one or more processors and a row by row format for the memory in the plurality of memory slices.


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