The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Mar. 28, 2011
Applicants:

Shih-tsung Chen, Taoyuan County, TW;

Wei Fang, Milipitas, CA (US);

Yu-tsorng Fu, Taipei County, TW;

Futang Peng, San Jose, CA (US);

Zhao-li Zhang, San Jose, CA (US);

Inventors:

Shih-Tsung Chen, Taoyuan County, TW;

Wei Fang, Milipitas, CA (US);

Yu-Tsorng Fu, Taipei County, TW;

Futang Peng, San Jose, CA (US);

Zhao-Li Zhang, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/00 (2006.01); G01N 21/95 (2006.01);
U.S. Cl.
CPC ...
G06T 7/001 (2013.01); G01N 21/9501 (2013.01);
Abstract

A method for promoting semiconductor manufacturing yield comprising the following steps and a computer readable medium encoded with a computer program implementing the method is provided. First, a processed layer is inspected to generate an inspected image with defects thereon. Next, the inspected image is aligned to an original design layout information of the processed layer. In addition, the defects are classified according to geometric features of the original design layout information of the processed layer and at least previous one layer and/or at least next one layer.


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