The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Sep. 02, 2013
Applicants:

Vijay Karamcheti, Los Altos, CA (US);

Kumar Ganapathy, Los Altos, CA (US);

Inventors:

Vijay Karamcheti, Los Altos, CA (US);

Kumar Ganapathy, Los Altos, CA (US);

Assignee:

Virident Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G11C 5/04 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G11C 5/04 (2013.01); G11C 29/76 (2013.01);
Abstract

In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.


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